The present invention relates generally to non-volatile memory devices and, more particularly, to a method and system of activating a plurality of wordline decoder circuits to transfer a predetermined high voltage to a plurality of wordlines during a test mode in flash electrically erasable programmable read-only memory (EEPROM) devices.
Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form Flash memory is typically constructed by fabricating a plurality of floating-gate transistors in a silicon substrate. A floating-gate transistor is capable of storing electrical charge on a separate gate electrode known as a floating gate that is separated by a thin dielectric layer from a control-gate electrode. Generally speaking, data is stored in a non-volatile memory device by the storage of an electrical charge in the floating gate.
Flash memories are in the form of a memory array that includes rows and columns of flash transistors, with each transistor being referred to as a memory cell that includes a control gate, a drain and a source. The control gates of the memory cells in each row of a sector are typically electrically interconnected to form wordlines such that a wordline decoder can direct a plurality of operational voltages to the wordlines. The drains of the memory cells in each column of a sector are typically electrically interconnected to form bitlines such that a bit line decoder directs a plurality of operational voltages to the bitlines. Generally, the sources of the memory cells in a sector are electrically interconnected to form a common sourceline and are controlled by a sourceline controller. As known in the art, the memory array is subdivided into sectors containing rows and columns of memory cells.
In recent years, the density of the memory array on a flash memory has increased dramatically. As the density of the memory array on a flash memory increases, it has become significantly more difficult to produce perfect flash memory. During fabrication of the flash memory, it is common for the memory array to include one or more defective memory cells. In an effort to improve production yield and flash memory reliability, it is known in the art to include spare or redundant memory cells on the flash memory to allow for repair by replacing the defective memory cells in the memory array.
During the fabrication process, the flash memory is tested using different screening techniques to identify defective cells that need replacement. Some of these testing techniques are designed to identify defects in the memory cells that otherwise would only gradually show themselves as the memory cells are operated within the operating specifications of the flash memory. Testing is also performed to verify that accessing parts of the memory array does not affect any other parts of the memory array. The testing is typically initiated by entering a test mode within the flash memory. When a particular test mode is entered, different voltages are applied to the bitline decoder, the wordline decoder and the sourceline controller depending on the testing that will be performed during the test mode.
The prior art methods and systems of performing testing that involve placing a predetermined high voltage on the wordlines in the flash memory have a known problem involving activating the wordline decoder to decode the wordlines to receive the predetermined high voltage. The wordline decoder is activated to transfer the predetermined high voltage to a respective plurality of wordlines when a pull-down transistor within the wordline decoder is activated to pull down an internal node within a respective plurality of wordline decoder circuits to approximately zero volts.
In the prior art, since the predetermined high voltage that needs to be transferred to the respective wordlines by the wordline decoder is first applied to the internal node of the respective wordline decoder circuits, the wordline decoder pull-down transistor must be capable of conducting a high current to a ground connection. To perform this function, the pull-down transistor must be made large thereby taking up area on the flash memory. In addition, as the number of respective wordlines required by the test mode to receive the predetermined high voltage increases, the transfer transistor needs to be made larger to accommodate the higher total current provided from the greater number of internal nodes of the respective wordline decoder circuits.
To that end, a need exists for a memory device with a method and system of applying a predetermined high voltage to a plurality of wordlines during a test mode that does not create high current when the wordline decoder is activated to transfer the predetermined high voltage to the wordlines.
The present invention discloses a method and system for applying a predetermined high voltage to a plurality of wordlines during a test mode that overcomes the problems associated with the prior art. The preferred flash memory includes a state machine, at least one wordline voltage supply circuit, at least one wordline decoder circuit and a plurality of wordlines. The state machine is electrically connected with the wordline voltage supply circuit and the wordline decoder circuits. The wordline decoder circuits are electrically connected with the wordline voltage supply circuits and the wordlines.
When a test mode is entered that requires a predetermined high voltage on a respective plurality of wordlines, the state machine activates the wordline voltage supply circuit and a plurality of wordline decoder circuits. In the preferred embodiment of the present invention, all of the wordlines in the flash memory are decoded during the test mode to receive the predetermined high voltage and, therefore, all the wordline decoder circuits are activated by the state machine. As known in the art, the state machine is used to control the overall operation of the flash memory in response to instruction sets that are received by the state machine. For purposes of the present invention, it is only necessary for those skilled in the art to understand that the state machine responds to test mode instruction sets to activate the wordline voltage supply circuit and the wordline decoder circuits.
During operation, when the state machine receives test mode instruction sets, the state machine sends electric signals to the wordline voltage supply circuit and the wordline decoder circuits. The electric signals from the state machine activate the wordline voltage supply circuit to begin supplying a first predetermined voltage to the wordline decoder circuits. The first predetermined voltage is from a supply-voltage (Vss) that is approximately zero volts. In addition, electric signals from the state machine activate the wordline decoder circuits to begin decoding the wordlines. As each respective wordline decoder circuit decodes respective wordlines, the first predetermined voltage supplied from respective wordline voltage supply circuits is transferred to the respective wordlines by the respective wordline decoder circuit.
As part of the activation by the state machine of the plurality of wordline decoder circuits, the state machine also activates a pull-down transistor that provides an electrical connection with a ground connection for the wordline decoder circuits. When the state machine activates a particular wordline decoder circuit, an internal node within the wordline decoder circuit is electrically connected through the pull-down transistor to the ground connection and is pulled down to zero volts. The internal node within the particular wordline decoder circuit is also electrically connected with the voltage provided by a respective wordline voltage supply circuit. Since at the time the particular wordline decoder circuit is activated, the first predetermined voltage supplied by the respective wordline voltage supply circuit is approximately zero volts, a negligible amount of current flows on the internal node through the pull-down transistor to the ground connection.
In the preferred embodiment, when the wordline decoder circuits have completed decoding the wordlines, the wordline voltage supply circuit begins supplying a second predetermined voltage to the activated wordline decoder circuits. The second predetermined voltage is from a supply voltage (Vcc) that is approximately 3.3 V. The wordline decoder circuits transfer the second predetermined voltage to the previously decoded wordlines. When the second predetermined voltage is supplied to the wordline decoder circuits, the internal node of each of the wordline decoder circuits is electrically isolated from the voltage being supplied by the wordline voltage supply circuits.
After the second predetermined voltage has been supplied to the wordline decoder circuits for at least ten microseconds, the state machine receives instruction sets and activates the wordline voltage supply circuit to supply a predetermined high voltage, which is at least 7 V in the preferred embodiment. The wordline voltage supply circuit that generates the predetermined high voltage is an external high voltage supply in the preferred embodiment Since the internal node of the activated wordline decoder circuits is electrically isolated from the predetermined voltage and the respective wordlines were previously decoded, the wordlines are already selected to receive voltage from the wordline voltage supply circuit. As such, the predetermined high voltage supplied by the wordline voltage supply circuit is transferred to the wordlines by the activated wordline decoder circuits and raises the wordlines to the predetermined high voltage.
At the conclusion of the test mode, the state machine receives instruction sets and activates the wordline voltage supply circuit to discontinue supplying the predetermined high voltage and again start supplying the second predetermined voltage. Since the wordlines have remained decoded by the activated wordline decoder circuits, the second predetermined voltage is transferred to the wordlines thereby reducing the magnitude of voltage on the wordlines from the predetermined high voltage. After the wordline decoder circuits have transferred the second predetermined voltage for at least ten microseconds, the wordline voltage supply circuit is activated to supply the first predetermined voltage and the wordline decoder circuits are deactivated to stop decoding the respective wordlines and exit the test mode.